A plurality of device cells, such as transistors and capacitors, may be integrated on a limited area of a semiconductor device according to a capacity of the semiconductor device. Such cells may be electrically separated from each other such that they can individually operate.
To electrically isolate the cells from each other, a local oxidation of silicon (LOCOS) process, in which a silicon substrate is recessed and then a field oxide layer is grown, and a trench isolation process, in which a trench is formed through an etching process and then an insulating material is filled in the trench, may be used. The trench isolation process may be suitable for a highly integrated semiconductor device where a spacing interval between cells (or unit elements) has been reduced.
According to related art, a semiconductor device may be fabricated by forming an isolation layer on a semiconductor substrate, sequentially forming a gate electrode and source/drain regions, and sequentially forming an interlayer dielectric layer, a contact, and a metal interconnection.
Hence, in the related art, a source/drain may be formed through ion implantation after forming a gate electrode and then a contact may be formed by selectively removing an interlayer dielectric layer.
A related art semiconductor device may have opposite-type dose doping due to misalignment when the source/drain regions are formed through an ion implantation process, for example after the gate electrode has been formed. Such a problem may lead to a leakage current, which may lower a reliability of a semiconductor device.
FIG. 1 is a photographic image showing an example test result, in which a contact spike has occurred, for example due to misalignment when patterning the contact through a related art method.
As shown in FIG. 1, according to a related art method for fabricating a semiconductor device, thick interlayer dielectric layer 106 may be formed after isolation layer 104 and a transistor have been formed. Part of interlayer dielectric layer 106 may then be selectively removed to form contact 114. However, if a misalignment occurs when forming the contact, a contact spike (see, for example, section A in FIG. 1) may be created. Such a contact spike may degrade the characteristics of the semiconductor device.